The invention is generally related to the field of MOSFET transistors and more specifically to a novel process to achieve controlled oxide growth over the polysilicon gate of a MOSFET transistor for improved transistor characteristics.
The formation of a sidewall offset spacer on the transistor polysilicon gate before the source-drain extension implant is often required to ensure proper gate-to-drain overlap in deep sub-micron CMOS transistors for improved device performance. It is often possible to obtain low source and drain resistance (Rsd) and gate-to-drain capacitance (Cgd) by co-optimizing the depth of the source-drain extension region and the thickness of the offset spacer. There are however, a number of drawbacks in using offset spacers in deep submicron CMOS transistors. Primarily, the use of the spacer increases process complexity and process variation. The spacer is often formed by depositing oxide or nitride films followed by a spacer etch. These extra steps increase process complexity and manufacturing cost. In addition to process complexity, it is very difficult to control the thickness and uniformity of the less than 200 A thick oxide and nitride films during the deposition process. Any variation in the film thickness directly affects the depth of the source-drain extension region and can affect the effective gate length (Leff) of the transistor. The extremely short gate lengths present in deep submicron CMOS transistors ( less than 0.1 um) make such variation in Leff unacceptable.
Recently, a heavy polysilicon gate re-oxidation process after the polysilicon gate etch process was proposed to replace the deposition and etch formation of the offset spacer. A polysilicon gate re-oxidation is required in a conventional CMOS process flow to repair the gate edge damage caused by the gate etch step. In a conventional CMOS process flow, the re-oxidation time and temperature were limited by the lateral oxidation of the gate oxide at the edge of the polysilicon gate. This lateral oxidation causes an increase in the gate oxide thickness and often results in the well known polysilicon xe2x80x9csmilexe2x80x9d effect. This increase in gate oxide thickness can greatly affect the submicron CMOS transistor performance. In this heavy polysilicon gate re-oxidation process approach, a nitrided gate oxide was used to minimize the polysilicon gate xe2x80x9csmilexe2x80x9d effect during the growth of about 200 A of oxide on the polysilicon gate during re-oxidation. This thick polysilicon oxide forms an offset spacer along the sidewall of the polysilicon gate. Using this approach, an offset spacer can be formed without much increase in the gate oxide thickness in the channel. This method also has better process uniformity and less process complexity than the spacer formed using film deposition and etch processes. Although this approach solves many problems related to spacer formation, it introduces another very serious problem. In this approach, a thick screen oxide of about 100 A was also grown on the semiconductor surface during the polysilicon re-oxidation. The presence of this thick screen oxide is undesirable for the shallow source-drain extension implant due to dopant loss in the screen oxide. This dopant loss results in a source-drain extension region depth that varies with the screen oxide thickness. These variations in the depth of the source-drain extension region can affect the effective gate length (Leff) of the transistor often rendering the transistor inoperable. In addition to the screen oxide thickness increase, the thick oxide film grown on the top surface of the polysilicon gate adds process complexity. In current submicron CMOS processes this oxide film has to be removed during processing. Additional thickness on top of polysilicon is such however that an addition oxide etch step has to be added for its removal. There is therefore a need for a method for sidewall spacer formation that is suitable for use in deep submicron CMOS transistors.
The instant invention is a method for forming sidewall structures on transistor gate structures. An embodiment of the invention comprises: providing a semiconductor substrate; forming a first film over said semiconductor substrate; implanting said first film with a first species; patterning said first film to form a transistor gate structure with a top surface and a plurality of side surfaces; implanting said transistor gate structure and said semiconductor substrate with a second species; and forming a dielectric film on said transistor gate structure wherein said dielectric film thickness on said top surface of said transistor gate structure and on silicon substrate is less than said dielectric film thickness on said plurality of side surfaces. A further embodiment comprises: providing a semiconductor substrate; forming a first film over said semiconductor substrate; implanting said first film with a first species; patterning said first film to form a transistor gate structure with a top surface and a plurality of side surfaces; incorporating nitrogen into said top surface of said transistor gate structure and said semiconductor substrate using remote plasma nitridation; and forming a dielectric film on said transistor gate structure wherein said dielectric film thickness on said top surface of said transistor gate structure is less than said dielectric film thickness on said plurality of side surfaces.